Clock Constraints — Part1 (Intro)
Welcome to a series on Clock Constraining. I’ll be discussing in detail how we constrain clocks in a design and the repercussions of doing so using examples. In the end, I’ll also be walking through some good practices to follow in constraining clocks. Hopefully this is informative to people who are starting with constraints or who want to understand why things are done the way they are. I’ll also try and keep this as intuitive as possible.
Disclaimer: This is not a bible on clock constraints. This is just a starting point. Feel free to reach out to me for any questions or feedback
Part1 of the series is a background on clock sources, clock definitions using commands & clock parameters. From Part2, we’ll dive deeper into the Clock Generator Module from clock definitions perspective.
Let’s get started!
Clock Definitions
Clock Definition Commands
Clock Characteristics
Where do we source clock constraints in the Physical Design Flow?
Clock constraints are sourced at multiple places in the Physical Design Flow. The most common stages of the flow are:
- Pre-synthesis
- Pre-CTS
- Post-CTS
- STA
Creating clock constraints that are common across the flow is a good practice to maintain consistency across different stages of the design. It also helps in correlation analysis of paths between different stages.
This part focused on the fundamentals of defining source / master clocks and their characteristics. In Part2, I walked through the following:
- Types of Generated Clocks in a design
- Divide_by
- Multiply_by
- Pulse Clocks
- Inverted Clocks
2. Implementation of Divided Clocks:
- Flop based divider
- Counter based divider
- EN signal of ICG for Pulse Clocks
Please feel free to reach out to me for any questions or feedback
