Clock Constraints — Part 2
Welcome back to Part2 of a series on Clock Constraints. As discussed in Part1, constraints are generated/created in a way that they’re scale-able across different stages of the flow — pre-synthesis , pre-placement , post-cts etc.
The external clocks and their frequencies will come as part of the datasheet or specification document, depending on how a company documents it during development phase.
You would also need to know what the duty cycle of the clocks are for defining generated clocks accurately. Wrong definitions could lead to incorrect clocks propagating through the design where you could end up optimizing for different conditions altogether , leading to re-work and re-spinning the designs and product timeline slips.
To be able to define generated clocks , often times you might have to trace through clock diagrams or RTL to understand different clock generator structures like divide_by or pulse clocks.
Things to know before defining generated clocks
- Clock Frequency of source and generated clocks
- Master Clock source out of which clocks are generated
- Pin/Port where the generated clocks are to be defined
- Clock relation between the source and generated clock
- Duty Cycle
Clock Divider Circuit — Divide by 2
create_generated_clock -name CLK_GEN_DIV2 \
-source [get_pins DIVBY2_FF/CLK] \
-master_clock CLKf \
-divide_by 2 \
-add
[get_pins DIVBY2_FF/Q]
Counter-based Divided Clocks
If multiple divided clocks are to be generated out of a single clock, counters are used to implement the division function: 2^n.
There are a number of implementations to count, but since this is not about implementation, I would just touch up on the basic overview.
The first thing is to identify how many divided clocks are needed out of a master clock. You could need divided by 2,4,8 for example. The number of counter bits required to implement this follows the rule:
2^n>= divisor
Say, the highest divisor is 8 from the above example, you’ll need 2^n>8. In this case, n = 4. For this case, counters can be any type of implementation — synchronous/asynchronous.
Note: Counters divide clock frequencies only for the following divisors: 2^n, meaning 2,4,8,16..
If you need a divide by 6, for example, below is one way to do it.
RTL snippet for the above implementation could look like below:
always @ (posedge clk) begin
if (!clear)
q0<=0;
q1<=0;
q2<=0;
else
q0<= ~q2;
q1<=q0;
q2<=q1;
end
Clock Definition on the counter output
create_generated_clock -name CLK_COUNTER_DIV4 \
-source [get_pins CLK_GEN_COUNTER_BIT[2]/CLK] \
-master_clock CLKf \
-divide_by 4 \
-add
[get_pins CLK_GEN_COUNTER_BIT[2]/Q]
Clock Div by n:
To implement a frequency divide by n , you will need a mod-n counter.
Size of the counter = # of bits satisfying 2^m>n. If n is 7, you need 3 mits (m=3)
- Mod-n counter that counts till n-1 before resetting to 0
- Flop
- OR gate
ICG
- If the EN signal is synchronous to the CLK of ICG, GCK will be the same frequency as CLK.
- However, if EN signal is CLK/2 , the generated clock will be a pulse clock as shown below
create_generated_clock -name CLK_GEN_PULSE \
-source [get_pins ICG/CLK] \
-master_clock CLKf \
-edges {1 2 5} \
-add
[get_pins ICG/GCK]
As you can see, the “-edges” option is used to model the above pulse clock.
It is important to trace what the EN signal is synchronized to. In most cases, EN signal is used to gate the logic downstream of the ICG.
In Part3, we’ll talk more on how these clocks are propagated, what are exceptions and why we need them.
